Field of the Invention
The present invention relates to a pattern formation method of forming a pattern on a substrate.
Description of the Related Art
As the degrees of micropatterning and integration of circuit patterns of semiconductor integrated circuits increase, it has become difficult for a conventional method of forming a circuit pattern by using two-dimensional pattern elements to faithfully transfer a designed pattern onto a substrate by using an exposure apparatus. Therefore, non-patent literature 1 has proposed a technique of forming a circuit pattern by using only one-dimensional pattern elements, that is, a so-called one-dimension layout technique. This one-dimension layout technique disclosed in non-patent literature 1 is a technique which forms a line and space pattern (L & S pattern) having a single pitch on a substrate beforehand, and forms a circuit pattern by partially removing the L & S pattern.
A pattern which is used to partially remove the L & S pattern is called a cut pattern. A plurality of elements (cut elements) of the cut pattern can be located at the intersections of a matrix grid (even grid) having the same pitch as that of the L & S pattern. That is, the pitches of the L & S pattern and even grid are equal. However, together with recent further increasing of degrees of micropatterning and integration of circuit patterns, it has become necessary to partially remove an L & S pattern formed to have a line width or pitch smaller than the resolution limit of an exposure apparatus by using a technique such as double exposure. In this case, if a cut pattern is so designed that a plurality of cut elements are located in accordance with the even grid, the line width and pitch of the plurality of cut elements become smaller than the resolution limit of an exposure apparatus. This may make it difficult to form the plurality of cut elements on an L & S pattern by using the exposure apparatus.    Non-Patent Literature 1: Michael C. Smayling et al., “32 nm and below Logic Patterning using Optimized Illumination and Double Patterning”, Proc. of SPIE, USA, SPIE, 2009, Vol. 7274, 7274K.    Non-Patent Literature 2: Shohei Yamauchi et al., “Applicability of double patterning process for fine hole patterns”, Proc. of SPIE, USA, SPIE, 2012, Vol. 8325, 832526.